1. Field of the Invention
This invention relates to self programming slave device controllers.
2. Description of the Prior Art
In a data processing apparatus, devices may be coupled together by a bus infrastructure to enable communication of data signals, address signals and control signals between the devices. The devices may include bus master devices, such as a core processor or a DMA (Direct Memory Access) controller, which can submit transactions to the bus, and bus slave devices, such as memory devices or an I/O (Input/Output) interface which can be accessed over the bus by the bus master devices.
The bus slave devices will typically be provided with a slave device controller which controls access to the slave device when access requests are received over the bus. A slave device controller may either form part of the slave device itself or may be provided as a discrete component. A slave device controller may control access to a slave device in accordance with one or more parameters, such as the number of clock cycles to be allocated to the access operation. These parameters may be configured at compile time, they may be programmable via a programming interface, or they may be selectable via an input. If performance characteristics, such as an access latency, of the slave device should change, the control of an access operation by the slave device controller may result in an inefficient use of system resources thereby wasting power, or alternatively may result in a failed access.